DRAMs (Dynamic RAMs), which are one type of RAMs (Random Access read write Memories), have a lower operation speed than SRAMs (Static RAMs), but are widely used as main storage devices for computers that require a large storage capacity due to its low costs and high degree of integration. On the other hand, MPUs (Micro Processing Units) have much higher operation speed than DRAMs, and some recent MPUs have a significantly improved operation speed; that is, their internal clock has a frequency of 50 to 200 MHZ. Thus, the difference in the operation speeds of DRAMs and MPUs as main storage devices is becoming larger and larger.
Consequently, to reduce the probability that the MPU accesses a memory via an external bus of a relatively low speed which operates in synchronism with an external clock of a frequency half to one-fourth of that of the internal clock, a cache memory (a primary cache) comprising an SRAM is generally provided inside the MPU. Moreover, to also reduce the probability of accessing the main storage device upon a cache miss of the primary cache, another cache memory (a secondary cache) comprising an SRAM is provided outside the MPU. The storage capacity of the secondary cache is eight to sixty-four times as large as that of the primary cache.
If such cache memories are provided, the MPU mainly accesses the main storage device in the unit of a plurality of data blocks (data reads or writes). In recent years, more and more DRAMs with a burst mode (for example, synchronous DRAMs, DRAMs with a burst EDO mode, and DRAMs conforming to the Rambus' specification) in which burst data (data read from or written to the DRAM) comprising a plurality of continuous data blocks is continuously and sequentially transferred have been used to eliminate the difference in the performance of MPUs and conventional DRAMs and to efficiently transfer data between MPUs and DRAMs. The burst mode serves to improve the bus usage efficiency to enable data to be transferred at apparently high speeds. As a result, the costs and size of computers can be reduced by, for example, using a DRAM with a burst mode as a secondary cache instead of a SRAM or as a main storage device to omit the secondary cache.
In fact, however, the DRAM must be refreshed periodically and a synchronously relative to external accesses. Thus, when an interruption for refreshing (hereafter referred to as a "refresh interruption") is carried out, refreshing is preferentially executed, and external accesses from, for example, MPUs are forced to wait for a long time, resulting in inconstant access time (the time from the input of an external request for a data read or write until data read in response to the read request is transferred or a response to the write request is returned).
In addition, the bit line connected to the storage cell of the DRAM must be precharged before a data read or write is carried out. Thus, if an attempt is made to immediately read data that has just been written to the DRAM in response to an external request, it takes long before the data can be read due to the amount of time required to precharge the bit line (that is, a large amount of cycle time is required for a data read immediately after a data write), also resulting in long access time.
Although various DRAMs (described below in detail) are currently used, no such DRAMs are guaranteed to have a constant access time as in SRAMs, and their access time depends upon the access timing. It has thus been difficult to use a DRAM as a secondary cache instead of a SRAM or to omit the secondary cache.
For example, DRAMs with a cache memory comprising a SRAM (RAMTRON EDRAMs or other cache DRAMs) have a constant access time if external accesses hit the cache memory. In this case, the DRAM array can be refreshed because it is not accessed. If, however, external accesses fail to hit the cache memory, the DRAM array will be directly accessed, and the access time will be long if a refresh interruption occurs at this point of time.
In addition, when a refresh interruption occurs, synchronous DRAMs and DRAMs with a burst EDO (Extended Data Out) mode described above abort the operation of a burst mode to sequentially execute the precharging of the bit line, the input of refresh addresses, and refreshing, thereby forcing the burst data to wait for transfer for a long time. If an attempt is made to immediately read data that has just been written, the cycle time will be long due to the amount of time required to precharge the bit line, resulting in the need of long access time to carry out reads immediately after data writes.
DRAMs conforming to the specification of Rambus Co., Ltd. (hereafter referred to as "Rambus-specified DRAMs") are also known as other DRAMs with a burst mode. Rambus-specified DRAMs basically use a sense amplifier as a cache to perform a burst operation, and external accesses are executed by sending 60 bits of request packet. If a hit does not occur in the cache and if a refresh interruption is being performed, the request packet is not accepted, and the request packet must be repeatedly transmitted every 100 nsec until it is accepted. Accesses to Rambus-specified DRAMs thus involve a large overhead in transmitting packets, so they are not suitable for applications that use a burst operation to read or write relatively short data and are mainly used for graphic processing that requires fast sequential accesses.
Pseudo SRAMs are known as DRAMs that can be accessed within a constant time regardless of external access timing. The basic idea of pseudo SRAMs is that the time required for a single cycle of a read or a write operation is set at a larger value, that the DRAM array is not accessed for a specified period of time or longer within a single cycle of a read or a write operation, and that when a refresh interruption is directed, the refreshing operation is completed within the above period of time. Accesses to these SRAMs require a very large amount of time, so they cannot be used instead of SRAMs that have a high operation speed.
On the other hand, various DRAMs with a burst mode as described above have a reduced bus usage efficiency in reading or writing burst data spanning a plurality of pages (spanning a plurality of lines with different row addresses). To improve the bus usage efficiency in reading or writing burst data spanning a plurality of pages, the applicant has already proposed a storage device pipelined into three sections: a section for decoding input row and column addresses (a row predecoder, a column predecoder, a refresh controller, and a burst mode decoder), a section for accessing a DRAM array 98 (a row decoder, a column decoder, and a sense amplifier), and a section for transferring data (a line buffer), as shown in FIG. 23 (Japanese Patent Application No. 7-317926, filed on Dec. 6, 1995).
Even with these storage devices, however, data that has just been written cannot be read immediately, and a read operation must wait until the precharging of the bit line ("PR" in FIG. 24) has been completed, as shown in FIG. 24 (FIG. 24 shows a four bit burst wherein after two continuous reads, a write is carried out, immediately after which a read is again executed). The cycle time is thus two clock longer (the period shown as "Idle" in FIG. 24) than in normal accesses, resulting in increased access time and reduced bus usage efficiency. In addition, although not shown, as in conventional examples, when a refresh interruption is directed, accesses must wait until the refreshing operation has been completed, resulting in longer access time.